The proliferation of client/server architectures has led to the increased concern to improve the performance of these architectures. A bottleneck to the client/server architecture is the I/O performance in accessing peripheral devices such as local area network (LAN) devices, small computer system interface (SCSI) devices, motion video devices, and the like.
The Peripheral Component Interconnect (PCI) bus is a bus architecture developed to address the I/O performance issues associated with personal computers. The PCI bus provides a direct connection to peripheral devices, such as LAN and SCSI devices, on the system backplane. The PCI bus also allows intelligent I/O devices, such as RAID controllers and the like, to be connected directly on the system backplane. This configuration is advantageous for improving the speed in accessing peripheral devices.
FIG. 1 illustrates a prior art data processing system 100 utilizing a RAID controller 102 that plugs into one of the host system's PCI bus slots and connects to one or more SCSI controllers 104A-104N. The RAID controller 102 includes a PCI bus interface 106 that interfaces between the host system's primary PCI bus 108 and a local CPU 110 located on a local bus 112. The PCI bus interface 106 enables data transfers between the primary PCI bus 108 and the local CPU 110 connected to the local bus 112. A memory 114 and one or more SCSI controllers 104A-104N are also connected to the local bus 112. The memory 114 is used to store data that is transmitted between a SCSI controller 104 and the primary PCI bus 108 and between the local CPU 110 and the SCSI controllers 104. A SCSI controller 104 can be an I/O processor that is coupled to one or more SCSI channels 115A-115N that include one or more peripheral devices 11 6A- 116N such as disk drives, CD-ROM and DAT tape drives, and the like.
In this particular controller design, all I/O activity utilizes the memory 114.
For example, data that is to be written to a particular SCSI controller 104 is transmitted from the primary PCI bus 108 and stored in the memory 114. The local CPU 110 initiates the appropriate actions to add parity to the data which is then stored in the intended SCSI controller 104. Data that is read from a SCSI controller 104 is stored in the memory until such time as the data can be transmitted on the primary PCI bus 108 to the host system (not shown). The use of the memory 114 for each I/O data transfer increases the traffic on the local bus 112. This increased bus traffic limits the use of the local bus 112 by the local CPU 110 and prevents it from accomplishing its tasks in a timely fashion.
FIG. 2 illustrates a second prior art data processing system 120 configured to overcome the I/O performance problem identified in the first prior art data processing system. There is shown a RAID controller 122 that is connected to the primary or host system PCI bus 124 and to a number of SCSI controllers 126A-126N by a secondary PCI bus 128. A SCSI controller 126 is connected to one or more SCSI channels 125A-125N which in turn are connected to one or more peripheral devices 127A-127N. The RAID controller 122 uses an Intel 80960 RP.TM. (i960 RP) processor 130 and a memory 132 to support data transfers between the host CPU (not shown) and the SCSI controllers 126. The memory is coupled to the processor 130 by a local bus 131. The i960 RP processor 130 provides a PCI-to-PCI bridge to interface between the primary 124 and secondary PCI 128 buses, a processor core, DMA support and interrupt handling, as well as other components.
The use of the local and secondary PCI buses in this configuration overcomes the bus traffic bottleneck experienced in the first prior art system. In addition, the use of the i960 RP processor 130 is advantageous since it frees the host system CPU of handling interrupt-driven 1/0 processing tasks as well as reduce the congestion on the primary PCI bus 124. However, a drawback with the RAID controller 122 in this configuration is that it is constrained to the performance limitations of the i960 RP. The i960 RP operates at a processor speed ranging from 33 Mhz to 66 Mhz which is substantially slower than host processor speeds which currently range between 233 Mhz-300 Mhz. Thus, the use of the i960 RP constrains the I/O bandwidth that can be achieved by the RAID controller 122.
Accordingly, there is a need for a mechanism for coupling intelligent I/O devices to the PCI bus in an efficient manner which can overcome these shortcomings.